The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
FIG. 1 shows an example phase lock loop (PLL) circuit 100 (or feedback loop) that includes a phase frequency detector (PFD) 102, a loop filter 104, and a voltage controlled oscillator (VCO) 106 with a divider 110. A reference clock signal RClk having a reference frequency FREF is provided to the PFD 102. The PFD 102 receives an output of the divider 110 and compares a phase of the output of the divider 110 to a phase of the reference clock signal RClk. The divider 110 can be an N frequency divider, which divides a PLL output clock signal PLLClk received from the VCO 106, where N is an integer. The PFD 102 generates an error signal based on the comparison. The error signal is filtered by the loop filter 104 (e.g., a low pass filter) and the filtered output of the loop filter 104 is provided to the VCO 106. The VCO 106 generates the PLL output clock signal PLLClk based on the output of the loop filter 104. The PLL output clock signal PLLClk has a frequency FVCO, which is equal to a product of the reference frequency FREE and a sum of a constant N and a ratio R (i.e. FVCO=FREF·(N+R)). In reference to circuit 100, the ratio R is achieved in this loop by modulating the divider ratio. In this case, the divider 110 is controlled by a delta sigma modulator in order to obtain a predetermined fraction.
As another example, FIG. 2 shows a PLL circuit 200 that includes a PFD 202, a loop filter 204, a VCO 206, and a feedback path 208 with a phase interpolator 210 and a divider 212. A reference clock signal RClk having a reference frequency FREE is provided to the PFD 202. The PFD 202 receives an output of the divider 212 and compares a phase of the output of the divider 212 to a phase of the reference clock signal RClk. The PFD 202 generates an error signal based on the comparison. The error signal is filtered by the loop filter 204 and the filtered output of the loop filter 204 is provided to the VCO 206. The error signal is used as a control signal to control operation of the VCO 206 in generation of the PLL output clock signal PLLClk.
The VCO 206 also generates multiple output clock signals (e.g., 2-16), each of which having the same frequency FVCO, but different phases. The more output clock signals generated, the better the resolution of the VCO 206. As an example, the output clock signals may include eight signals having respectively different phases (e.g., ph0-ph7), where the phases refer to different phases of a same period. The eight output clock signals may be equally spaced apart in phase, such that differences in phases between consecutive pairs of the eight output clock signals are the same. Each of the eight output clock signals may have, for example, a phase delay time ΔT·(i+1), where i is the number of the output clock signal (e.g., i=0, 1, . . . , 7) and ΔT is the difference in phase between each consecutive pair of the output clock signals.
The phase interpolator 210 receives and interpolates the output clock signals to produce an interpolated output signal. As an example, the interpolated output signal may be a weighted sum of the output clock signals. The divider 212 may be an N frequency divider and divides the PLL output clock signal PLLClk received from the VCO 206 to provide the output received by the PFD 302, where N is an integer.